Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

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Introduction

Hey it's a me again @drifter1!

Today we continue with the Logic Design series on SystemVerilog in order to talk about Command Line Arguments & Dynamic Casting. These are also the final topics that we had to cover before getting into Examples...

So, without further ado, let's get straight into it!

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Command Line Arguments

When anything (which includes even a single variable's value) is tweaked within a testbench, the testbench will need to be recompiled each time. In order to allow small tweaks, without the need of recompilation, SystemVerilog allows information to be passed as arguments from the command line.

Passing Arguments

The command line arguments are optional. They start with the + character, followed by an identifier in caps and an = sign. After the = sign comes the value to be used. If left unspecified the value will be an empty string. But, the = can't be missing, as otherwise the argument will not be recognized. Additionally, there should not be any space between these characters.

For example:

+N=100
+STR=test
+FLAG=

Note: Strings can be passed with and without double quotes ("").

Using Arguments

From within the SystemVerilog code, these command line arguments are accessible through two $plusargs system functions:

$test$plusargs(arg_string)

$value$plusargs(arg_string, var)

The first one is used when the value of the argument is not required, but only it's "existence" should be checked. This can be easily used as a form of flag for enabling / disabling code. A zero is returned when the characters specified don't match any argument.

For example:

if ($test$plusargs("FLAG"))
    // code

The second function requires some kind of string formatting to be specified. Similar to the $display system task.

For example:

$value$plusargs("N=%d", n)

would retrieve the value 100 specified in the argument N and pass it to the variable n.

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Dynamic Casting

Sometimes we may want to assign data types, which normally would be invalid using =. For that purpose SystemVerilog provides the $cast method, which is used for dynamic casting.

It can be used as both a task and a function, which changes it's behavior a bit. The difference is that the function returns a 0 when the cast is illegal (1 when it's legal), whilst the task causes an runtime error.

The syntax is:

$cast (destination, source);

For example, this can be used for assigning an integer value to an enumerated value:

typedef enum { ONE=1, TWO=2, THREE=3 } Nums;

Nums num;

$cast (num, 1 + 2);

In some simulators a simple num = 1 + 2 may trigger an compilation warning and maybe even an error.

Putting a value of let's say 4 would of course be invalid in that case.

The $cast method is also useful for casting between classes which are related in Polymorphism.

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RESOURCES:

References

1. https://www.chipverify.com/systemverilog/systemverilog-tutorial
2. https://www.asic-world.com/systemverilog/tutorial.html

Images

1. https://www.flickr.com/photos/creative_stock/5227842611

Block diagrams and other visualizations were made using draw.io

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Previous articles of the series

Verilog

• Introduction → Basic Syntax, Data Types, Operators, Modules
• Combinational Logic → Assign Statement, Always Block, Control Blocks, Gate-Level Modeling and Primitives, User-Defined Primitives
• Combinational Logic Examples → One Circuit - Four Implementations, Encoder, Decoder, Multiplexer
• Sequential Logic → Procedural Blocks (Initial, Always), Blocking and Non-Blocking Assignments, Statement Groups
• Sequential Logic Examples → Flip Flops (DFF, TFF, JKFF, SRFF), N-bit Counter, Single-Port RAM
• Finite-State Machines → Finite-State Machine (FSM), FSM Types, State Encoding, Modeling FSMs in Verilog
• Finite-State Machine Examples → Moore FSM Example (1 and 2 always blocks), Mealy FSM Example (1, 2 and 3 always blocks)
• Testbenches and Simulation → Testbenches (DUT / UUT, Syntax, Test Cases), System Tasks, Simulation Tools
• Combinational Logic Testbench Example → Half Adder Implementation, Testbench and Simulation
• Sequential Logic Testbench Example → Sequence Detector FSM Implementation, Testbench and Simulation
• Functions and Tasks → Function and Task Syntax, Calling, Rules, Examples
• Module Parameters and Generate Block → Parameterized Module (Parameters, Instantiation and Overriding Parameters), Generate Blocks (For, If, Case)
• Compiler Directives → Summary of Verilog's Compiler Directives (Include, Macros, Timescale, Conditional Compilation, etc.)
• Switch Level Modeling → Transistors, Switch Primitives (NMOS, PMOS, CMOS, Bidirectional, Resistive), Signal Strengths

SystemVerilog

• From Verilog To SystemVerilog → Data Types, Arrays, Structures, Operators and Expressions
• Control Flow → Additional Procedural Blocks, Loops, Conditional Statements, Functions and Task Features
• Processes → Fork - Join in Verilog and SystemVerilog, Process Control (wait fork, disable fork)
• Events → Interprocess Communication, Events (Definition, Triggering, Waiting, Sequencing, Merging, as Arguments)
• Semaphores and Mailboxes → Semaphores (Creation, Methods), Mailboxes (Definition, Methods)
• Interfaces (part 1) → Interfaces (Definition, Port and Signal Lists, Instantiation), Modports
• Interfaces (part 2) → Parameters, Tasks and Functions (Importing, Exporting), Clocking Blocks (Input and Output Skews)
• Classes (part 1) → Classes (Definition, Constructor Function, Creating Objects, Accessing Class Members, Static and Constant Class Members, Arrays)
• Classes (part 2) → Copying Objects (Shallow and Deep Copy), Inheritance, Polymorphism, Virtual Methods
• Classes (part 3) → Parameterized Classes, Out-of-Block Method Declaration, Data Accessibility, Abstract / Virtual Classes
• Program Blocks → Design and Testbench, Program Block (Reactive Region, Allowed Constructs)
• Packages → Design Hierarchy, Packages (Definition, Importing, Definition Collision)
• Constraints and Randomization → Testing and Verification, Random Variables (Standard, Random-Cyclic), Randomize Method (Constraint and Random Mode, Pre / Post Randomize)
• Constraint Blocks → Constraint Blocks (Syntax, Rules), External (Explicit, Implicit), Static, Soft and In-Line Constraints
• Constraint Types (part 1) → Simple Expressions, Set Membership (Inside Operator, Range, Set, Inverted), Weighted Distributions (Dist Operator, := and :/)
• Constraint Types (part 2) → Conditional Relations (Implication Operator, If-Else), Iterative Constraints, Solve - Before, Random Case
• Functional Coverage → Functional Coverage (Limitations, Types), Covergroups (Sampling, Coverage Points, Coverpoint Bins, Conditional Coverage, Cross Coverage, Coverage Options)
• Assertions → Assertions, Immediate Assertions, Concurrent Assertions (Boolean, Sequence, Property, Assert), Assume, Cover and Expect

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Final words | Next up

And this is actually it for today's post!

From next time on we will start getting into Examples. But, that might take a while as I'm not too sure about where to start...

See Ya!

Keep on drifting!