#verilog

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serpent7776

2y

Fizzbuzz in #verilog

$ 0.000

0

drifter1

5y

Logic Design - Circuit Examples in SystemVerilog

Logic Design - Circuit Examples in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic

$ 2.379

64

drifter1

5y

Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Command Line Arguments & Dynamic Casting. These are

drifter1

5y

Logic Design - Assertions in SystemVerilog

Logic Design - Assertions in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Assertions. So, without further ado, let's get straight

darth-cryptic

3d

Genealogy: Nicholas Carew (1363-1432)

Genealogy: Nicholas Carew (1363-1432)

I am posting some random bits of my genealogy research here with the goal of eventually creating a linked family tree on Hive. Subject: Nicholas Carew (1363-1432)

drifter1

5y

Logic Design - Functional Coverage in SystemVerilog

Logic Design - Functional Coverage in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Functional Coverage. So, without further ado, let's get

drifter1

5y

Logic Design - Constraint Types in SystemVerilog (part 2)

Logic Design - Constraint Types in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. This is part 2. You can

drifter1

5y

Logic Design - Constraint Types in SystemVerilog (part 1)

Logic Design - Constraint Types in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. The topic will be split

drifter1

5y

Logic Design - Constraint Blocks (SystemVerilog)

Logic Design - Constraint Blocks (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraint Blocks. Let's note that we will not cover

rlathulerie

2d

Pato guisado en salsa de cilantro y culantro | Duck stew in cilantro and culantro sauce 🍗🍽😋

Pato guisado en salsa de cilantro y culantro | Duck stew in cilantro and culantro sauce 🍗🍽😋

Hello gente de Hive, feliz inicio de semana! Hoy les traigo una receta de esas que entran en la categoría de comida reconfortante, una de esas que sientes que te abrazan el alma en cada bocado y confortan

drifter1

5y

Logic Design - Constraints and Randomization (SystemVerilog)

Logic Design - Constraints and Randomization (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraints and Randomization. So, without further ado,

drifter1

5y

Logic Design - Packages in SystemVerilog

Logic Design - Packages in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Packages. So, without further ado, let's get straight

drifter1

5y

Logic Design - Program Blocks in SystemVerilog

Logic Design - Program Blocks in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the Program Block. So, without further ado, let's get

drifter1

5y

Logic Design - Classes in SystemVerilog (part 3)

Logic Design - Classes in SystemVerilog (part 3)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 3 and also the final part!

dead-pets

1d

029 Grim Bond

Dead Pets Society is a passion project of @honeydue and @godfish. It is about yearning for the other. About the desire to subvert meanings and look at the world through different eyes. To see things anew.

drifter1

5y

Logic Design - Classes in SystemVerilog (part 2)

Logic Design - Classes in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 2 and so I highly suggest

drifter1

5y

Logic Design - Classes in SystemVerilog (part 1)

Logic Design - Classes in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to start getting into Classes. The topic will be split into multiple

drifter1

5y

Logic Design - Interfaces in SystemVerilog (part 2)

Logic Design - Interfaces in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to continue with Interfaces. This is part 2 and so I highly suggest

drifter1

5y

Logic Design - Interfaces in SystemVerilog (part 1)

Logic Design - Interfaces in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Interfaces. The topic will be split into two parts! So, without

cabzphoto

Black And White

5d

TAKANAKUY: THE CATHARSIS OF THE ANDES / LA CATARSIS DE LOS ANDES [ENG-ESP]

TAKANAKUY: THE CATHARSIS OF THE ANDES / LA CATARSIS DE LOS ANDES [ENG-ESP]

“The Andean ritual where grievances are settled and life is celebrated amidst the struggle.”

drifter1

5y

Logic Design - Semaphores and Mailboxes (SystemVerilog)

Logic Design - Semaphores and Mailboxes (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Semaphores and Mailboxes, which are the two other interprocess

drifter1

5y

Logic Design - Events (SystemVerilog)

Logic Design - Events (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Events, which are one of the three main interprocess communication

drifter1

5y

Logic Design - Processes (SystemVerilog)

Logic Design - Processes (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Processes. So, without further ado, let's dive straight into

drifter1

5y

Logic Design - Control Flow (SystemVerilog)

Logic Design - Control Flow (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover some of the additional Control Flow that it provides. Many