[Edit of Image1]
Hey it's a me again @drifter1!
Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. This is part 2. You can check out the 1st part here.
So, without further ado, let's get straight into it!
SystemVerilog provides two styles for declaring conditional relations: implication and if-else. These are basically ways of declaring that constraints should only be active when specific conditions are met.
The implication operator -> is used for specifying a conditional relationship between two expressions. The expressions in that case are the condition and constraint. So, the constraint expression (RHS) is only considered (or active) when the condition expression (LHS) is true.
The syntax is as follows:
constraint c_impl { cond_expr -> const_expr }
For example:
constraint c_impl { a == 1 -> b > 10; }
The constraint (b > 10) is only active when a equals 1.
Of course, it's possible to specify multiple constraints by enclosing them in {}.
A big limitation of the implication operator though is that it doesn't provide a way of specifying what happens when the condition is false.
When a different set of constraints should be active when a condition is true or false then the if-else constraint needs to be used instead.
Let's note that multiple statements have to be enclosed in {} and not in begin end as in the usual if-else conditional statement. When only one statement follows the if or else, the {} can be omitted.
Nesting multiple if-else statements or adding else if sections is of course also allowed.
For example:
constraint c_if {
if (a == 1)
b > 10;
else
b < 10;
}
Up to this point, we only saw how normal variables can be constrained. In order to specify constraints for arrays, some form of iterative constraints is required. That's exactly what SystemVerilog provides!
In the case of static arrays, a simple foreach loop is sufficient for specifying a constraint for every single element.
For example, consider a static array named arr. Specifying that the value of each element should be equal to its index is as simple as:
constraint c_array {
foreach (arr[i])
arr[i] == i;
}
The same foreach loop can also be used in the case of dynamic structures (arrays or queues). But, because such structures don't have a size at the time of declaration, their size must be set directly or as a part of some set of constraints before randomization.
A queue can be constrained like this:
rand int queue [$]; // size unknown
// size constraint
constraint c_qsize { queue.size() == 10; }
// iterative constraint
constraint c_queue {
foreach (queue[i])
queue[i] == i;
}
A dynamic array can be constrained like this:
rand int darr []; // size unknown
// iterative constraint
constraint c_array {
foreach (darr[i])
darr[i] == i;
}
...
// assign size
darr = new[10];
The last statement has to be called sometime before calling randomize(). This, it could even be part of the class constructor:
function new()
darr = new[10];
endfunction
Nesting multiple foreach loops constraining static multidimensional arrays is a piece of cake. A loop variable is specified for each direction.
For example:
constraint c_mdarray {
foreach (mdarr[i][j])
mdarr[i][j] inside {[1 : 10]};
}
But, that's not the case for dynamic multidimensional arrays. For dynamic arrays, a size has to be assigned for each dimension. This can easily become tricky!
The solver always assures that the random values are selected uniformly. In other words, by default, the probability of each and any legal value is the same as all values are determined together.
Last time we covered the dist operator which allows us to weight the legal value set. Additionally, SystemVerilog also provides the solve before feature. Using it we basically specify some form of variable ordering. In other words, the variables specified in the solve before are not determined together but one after the other. The value given to the first one affects the legal range of the next one. Only rand is allowed, as randc variables are always solved first. Lastly, circular dependencies are also forbidden.
For example, consider the following random variables and their corresponding implication constraint:
rand bit a;
rand bit [1 : 0] b;
constraint c_ab { a -> b == 1; }
When a is 0, b can take any of the 4 legal values. But, when a is 1, b can only be equal to 1. So, there's a total of 5 combinations. Each choice having an equal probability of 20%.
Let's now include solve before, so that the value of a is chosen independently and before b.
constraint c_ab2 {
a -> b == 1;
solve a before b;
}
Now, the probability of a being either 0 or 1 is 50%. The value of b depends on the value of a and thus b now has a 62.5% chance of being 1, and 12.5% of being 0, 2 or 3.
So, having a = 1 and b = 1 is of 50% probability instead of the 20% that we had before. And the remaining 4 choices now each have a probability of 12.5%.
Sometimes, we may want to pick one random statement out of many statements. In that case the randcase construct can be useful. Each case is also given a weight, allowing us to specify the probability of each choice.
The syntax is:
randcase
weight : statement;
...
endcase
Of course, this is not a constraint by itself, but constraints and randomization can be defined in the individual choices!
Block diagrams and other visualizations were made using draw.io
And this is actually it for today's post!
Now we only have Assertions and Functional Coverage left...in terms of bigger concepts that is. And there are also some smaller topics such as Type Casting or Command-Line Input.
Of course, I also haven't forgotten about Examples! There will be quite a few after we introduce all the features that SystemVerilog provides us with.
See Ya!
Keep on drifting!