Logic Design - Classes in SystemVerilog (part 1)

[Edit of Image1]

Introduction

Hey it's a me again @drifter1!

Today we continue with the Logic Design series on SystemVerilog in order to start getting into Classes. The topic will be split into multiple parts!

So, without further ado, let's dive straight into it!

Classes

SystemVerilog can't be OOP without having objects. A new user-defined datatype class is thus introduced, which allows objects to be dynamically created, deleted, assigned and accessed like in C++. Such classes group together data (properties) and tasks/functions (methods) that operate on the data. These properties and methods are commonly referred to as members of the class.

Class Definition

A class can be defined in any module or program (that we haven't discussed yet though), and is enclosed within the class and endclass keywords, as shown below.

class className;
    // properties
    // methods
endclass

Constructor Function

Objects of the class are created using the new() function, which is called a constructor. There can only be one constructor per class, the constructor has to be a function and not a task, and it doesn't return anything. It's common to initialize the data to default values in such a function, as shown below:

function new (property1 = default1, property2 = default2, ...);
    this.property1 = property1;
    this.property2 = property2;
    ...
endfunction

The keyword this refers to the properties/methods within the class.

Creating Objects

The quickest way of creating an object of a class is the following:

className instanceName;

instanceName = new();

The individual parameters of the new() function can of course be overridden, otherwise the defaults will be used instead.

When the new() function is not called, the object is undefined or of type null, which can be used in conditional statements in order to avoid a null pointer exceptions/dereferences.

Two objects can also point to the same instance, as shown below.

className instanceName2;

instanceName2 = instanceName;

With that the 2nd instance points to the contents of the 1st instance.

Accessing the Class Members

The properties and methods of an object (instance) of the class are accessed using the dot (.) operator.

instanceName.property1

instanceName.method1()

Static Class Members

In order share properties easily across different instances, SystemVerilog provides the static keyword. This keyword has to be added in front of any property that we wish to share. That way, any change will be reflected to the other instances.

Constant Class Members

Making properties read-only (constants) is also easy, and is done by adding the const keyword in the declaration. If the constant's initial value is added as part of the declaration, the constant is global and cannot be assigned to a different value anymore. But, it's possible to not include any initial value in the declaration. That way, the constant's value can be assigned in the corresponding class constructor function, becoming a sort of instance-dependent constant.

Arrays of Classes

Arrays of any class are created similar to any other included data type (int, string etc.).

For example, a simple, static, one-dimensional array can be defined as:

className arrayName [N];

RESOURCES:

References

Images

https://www.flickr.com/photos/creative_stock/5227842611

Block diagrams and other visualizations were made using draw.io

Previous articles of the series

Verilog

Introduction → Basic Syntax, Data Types, Operators, Modules
Combinational Logic → Assign Statement, Always Block, Control Blocks, Gate-Level Modeling and Primitives, User-Defined Primitives
Combinational Logic Examples → One Circuit - Four Implementations, Encoder, Decoder, Multiplexer
Sequential Logic → Procedural Blocks (Initial, Always), Blocking and Non-Blocking Assignments, Statement Groups
Sequential Logic Examples → Flip Flops (DFF, TFF, JKFF, SRFF), N-bit Counter, Single-Port RAM
Finite-State Machines → Finite-State Machine (FSM), FSM Types, State Encoding, Modeling FSMs in Verilog
Finite-State Machine Examples → Moore FSM Example (1 and 2 always blocks), Mealy FSM Example (1, 2 and 3 always blocks)
Testbenches and Simulation → Testbenches (DUT / UUT, Syntax, Test Cases), System Tasks, Simulation Tools
Combinational Logic Testbench Example → Half Adder Implementation, Testbench and Simulation
Sequential Logic Testbench Example → Sequence Detector FSM Implementation, Testbench and Simulation
Functions and Tasks → Function and Task Syntax, Calling, Rules, Examples
Module Parameters and Generate Block → Parameterized Module (Parameters, Instantiation and Overriding Parameters), Generate Blocks (For, If, Case)
Compiler Directives → Summary of Verilog's Compiler Directives (Include, Macros, Timescale, Conditional Compilation, etc.)
Switch Level Modeling → Transistors, Switch Primitives (NMOS, PMOS, CMOS, Bidirectional, Resistive), Signal Strengths

SystemVerilog

From Verilog To SystemVerilog → Data Types, Arrays, Structures, Operators and Expressions
Control Flow → Additional Procedural Blocks, Loops, Conditional Statements, Functions and Task Features
Processes → Fork - Join in Verilog and SystemVerilog, Process Control (wait fork, disable fork)
Events → Interprocess Communication, Events (Definition, Triggering, Waiting, Sequencing, Merging, as Arguments)
Semaphores and Mailboxes → Semaphores (Creation, Methods), Mailboxes (Definition, Methods)
Interfaces (part 1) → Interfaces (Definition, Port and Signal Lists, Instantiation), Modports
Interfaces (part 2) → Parameters, Tasks and Functions (Importing, Exporting), Clocking Blocks (Input and Output Skews)

Final words | Next up

And this is actually it for today's post!

Next time we will continue on with more on Classes...

See Ya!

Keep on drifting!

Logic Design - Classes in SystemVerilog (part 1) | Ecency