Logic Design - Switch Level Modeling [Verilog]

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Introduction

Hey it's a me again @drifter1!

Today we continue with the Logic Design series on Verilog to cover Switch Level Modeling, which allow us to take the HDL code into the analog and transistor levels. Such design is rarely used nowadays, as higher levels of abstraction such as RTL are basically required when implementing complex circuitry, but we will still cover it for the sake of completeness.

So, without further ado, let's dive more into it!

Switch Level Modeling

When modeling in the switch level, we basically are somewhere between the logic and analog transistor levels of abstraction. We are thus describing the interconnection of transmission gates, such as individual MOS and CMOS transistors.

Transistors

Transistors are either conducting electricity or not, which can be thought of as a switch which is either on or off. The actual range of currents and voltages is of course analog, but is commonly split into discrete values known as signal strengths.

Verilog allows for direct Transistor Level Modeling as well, but this is way to low-level. Even Switch Level Modeling is basically useless, and very few designers still use it. But, it gives us an insight to how Hardware is actually structured (which for me was quite an interesting topic during my studies).

Switch Primitives

As we already know, Verilog uses a 4 value logic system. Switch inputs and outputs therefore take any of these four values: 0, 1, Z, X.

A switch is unidirectional or bidirectional, and can be resistive or non-resistive to a particular input. A NMOS transistor can be modeled as a switch that is on with a positive gate, whilst a PMOS transistor can be modeled to be on with a negative gate.

In the context of Transistors:

• Switching ON means logic values flow from the input transistor to the switch input
• Switching OFF means that the transistor output is always Z, regardless of the input value
• A unidirectional transistor passes its input value only to its output when switched on, whilst a bidirectional transistor conducts both ways
• A resistive transistor reduces the strength of the input logic when passing it to its output

MOS Switches

The two types of MOS switches are defined by the keywords nmos and pmos. They are Verilog primitives, similar to the gate primitives, and can thus be instantiated as follows:

nmos (out, data, control);
pmos (out, data, control);

The output, out, is determined by the values of the data and control input signals.

Depending on the combination of the data and control signals, the output will be either 1 or 0 or Z.

A NMOS switch conducts (data goes to out) when its control signal is 1, otherwise if the control signal is 0 the output will be Z. On the other hand, the PMOS switch conducts when the control signal is 0.

CMOS Switches

A CMOS switch, which is the combination of a PMOS and a CMOS switch, can be modeled using the cmos keyword. Its instantiated as follows:

cmos (out, data, ncontrol, pcontrol);

which is the same as writing:

nmos (out, data, ncontrol);
pmos (out, data, pcontrol);

The ncontrol and pcontrol are usually complementary to each other. Thus if ncontrol is 1, pcontrol will be 0, and the switch will be conducting. If ncontrol is 0 and pcontrol is 1, the output will be the high impedance, Z.

Bidirectional Switches

NMOS, PMOS and CMOS conduct from the the drain to the source, and are thus unidirectional. But, sometimes bidirectional can also be useful. In these cases, the tran, tranif0 and tranif1 keywords can be used, which instantiate the corresponding primitives:

tran (io1, io2);
tranif0 (io1, io2, ctrl);
tranif1 (io1, io2, ctrl);

where:

• tran switch : basically a buffer between the io1 and io2 signals, with either one being the driver
• tranif0 switch : connects the two signals only if the control signal is 0, otherwise the non-driver signal gets the high impedance value Z
• tranif1 switch : connects the two signals only if the control signal is 1

Resistive Switches

Adding an "r" in front of the name of most of the other switches makes them resistive. For example, a resistive cmos is rcmos, whilst a resistive tranif0 would be rtranif0.

Power and Ground

In order to model the VDD and ground parts of an electronic circuit, the pre-defined supply1 and supply0 net data types can be used.

supply1 vdd;
supply0 gnd;

Logic Strengths

In addition to the logic value, Verilog also specifies a logic strength, which basically is the ability of acting as the driver signal. In higher levels of abstraction this value is always "strong" by default, but when getting into the low-level things get more complicated.

There are two kinds of logic strengths: strength for 0 and strength for 1. That logic strength takes an integer value from 1 to 7, which indicates the relative strength, with 7 being the highest. For a value of Z, the strength is HiZ0 or HiZ1, whilst X is ambiguous and can be in either side.

For more information check out Ref4!

RESOURCES:

References

1. http://www.asic-world.com/verilog/veritut.html
2. https://www.chipverify.com/verilog/verilog-tutorial
3. https://www.javatpoint.com/verilog
4. http://www.cs.nthu.edu.tw/~tcwang/4120-spring04/lec5.pdf

Images

1. https://www.flickr.com/photos/creative_stock/5227842611

Block diagrams and other visualizations were made using draw.io

Previous articles of the series

• Introduction → Basic Syntax, Data Types, Operators, Modules
• Combinational Logic → Assign Statement, Always Block, Control Blocks, Gate-Level Modeling and Primitives, User-Defined Primitives
• Combinational Logic Examples → One Circuit - Four Implementations, Encoder, Decoder, Multiplexer
• Sequential Logic → Procedural Blocks (Initial, Always), Blocking and Non-Blocking Assignments, Statement Groups
• Sequential Logic Examples → Flip Flops (DFF, TFF, JKFF, SRFF), N-bit Counter, Single-Port RAM
• Finite-State Machines → Finite-State Machine (FSM), FSM Types, State Encoding, Modeling FSMs in Verilog
• Finite-State Machine Examples → Moore FSM Example (1 and 2 always blocks), Mealy FSM Example (1, 2 and 3 always blocks)
• Testbenches and Simulation → Testbenches (DUT / UUT, Syntax, Test Cases), System Tasks, Simulation Tools
• Combinational Logic Testbench Example → Half Adder Implementation, Testbench and Simulation
• Sequential Logic Testbench Example → Sequence Detector FSM Implementation, Testbench and Simulation
• Functions and Tasks → Function and Task Syntax, Calling, Rules, Examples
• Module Parameters and Generate Block → Parameterized Module (Parameters, Instantiation and Overriding Parameters), Generate Blocks (For, If, Case)
• Compiler Directives → Summary of Verilog's Compiler Directives (Include, Macros, Timescale, Conditional Compilation, etc.)

Final words | Next up

And this is actually it for today's post!

From next time on we will start getting into SystemVerilog!

See Ya!

Keep on drifting!