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latest #hdl created topics | Ecency

piotrgrafik

2025-01-06 08:11

LDL vs. HDL: The Battle of the Cholesterols Explained

LDL vs. HDL: The Battle of the Cholesterols Explained

Okay, so cholesterol might sound like the bad guy in your body’s health drama, but it’s actually a VIP player that just needs a little balance. The stars of this show are two types of lipoproteins: LDL

$ 3.622

45

drifter1

2021-11-25 13:31

Logic Design - From Verilog To SystemVerilog

Logic Design - From Verilog To SystemVerilog

The first part of another series where we will be extending our Verilog knowledge into SystemVerilog

$ 2.250

19

drifter1

2021-11-16 16:56

Logic Design - Switch Level Modeling [Verilog]

Logic Design - Switch Level Modeling [Verilog]

Modeling in the transistor / switch levels using Verilog

drifter1

2021-11-15 10:57

Logic Design - Compiler Directives [Verilog]

Logic Design - Compiler Directives [Verilog]

In-depth usage guide on the Compiler Directives of Verilog

soyunasantacruz

Throwback Thursday

2026-08-14 00:13

Celebrating My 36th Birthday 🎂 | Birthday Initiative

Celebrating My 36th Birthday 🎂 | Birthday Initiative

When I turned 36, I felt far too old to do things that young people do, and far too young to do things that older people do. My thirties were a wonderful time in my life because I felt healthy and confident;

drifter1

2021-11-11 10:58

Logic Design - Module Parameters and Generate Block [Verilog]

Logic Design - Module Parameters and Generate Block [Verilog]

In-depth guide to Module Parameters and the Generate Block in Verilog HDL

drifter1

2021-11-09 16:39

Logic Design - Functions and Tasks [Verilog]

Logic Design - Functions and Tasks [Verilog]

In-depth guide on using Functions and Tasks in Verilog

drifter1

2021-11-03 12:11

Logic Design - Sequential Logic Testbench Example [Verilog]

Logic Design - Sequential Logic Testbench Example [Verilog]

A simple, full-on example of implementing, simulating and verifying a sequence detector FSM

drifter1

2021-10-29 10:01

Logic Design - Combinational Logic Testbench Example [Verilog]

Logic Design - Combinational Logic Testbench Example [Verilog]

A simple, full-on example of implementing, simulating and verifying a half adder circuit

nabbas0786

2026-08-14 00:47

Why Quaid-e-Azam's 1947 Vision Is Vital for Independence Day

Why Quaid-e-Azam's 1947 Vision Is Vital for Independence Day

Independence day and Vision of Quaid-e-Azam has already told us all this, and the solution to all these issues will be found in implementing Islamic laws.

drifter1

Programming & Dev

2021-10-20 09:06

Logic Design - Testbenches and Simulation in Verilog

Logic Design - Testbenches and Simulation in Verilog

In-depth guide on testbench design using Verilog

drifter1

Programming & Dev

2021-10-04 12:15

Logic Design - Finite-State Machine Examples in Verilog

Logic Design - Finite-State Machine Examples in Verilog

In-depth examples on FSM modeling using the Verilog HDL

drifter1

Programming & Dev

2021-09-21 09:35

Logic Design - Finite-State Machines in Verilog

Logic Design - Finite-State Machines in Verilog

In-depth guide to modeling any kind of FSM in Verilog using always blocks

drifter1

Programming & Dev

2021-08-16 16:47

Logic Design - Sequential Logic Examples in Verilog

Logic Design - Sequential Logic Examples in Verilog

Full-on sequential logic implementation examples in Verilog (Flip Flops, Counters and RAM)

tonyz

2026-08-01 19:50

Bretagne, France.

Bretagne, France.

We took the car to Bretagne. Nice trip, starting point Amsterdam.

drifter1

Programming & Dev

2021-07-26 10:15

Logic Design - Sequential Logic in Verilog

Logic Design - Sequential Logic in Verilog

An article on the various important things to consider when writing sequential logic using Verilog

drifter1

Programming & Dev

2021-07-13 15:20

Logic Design - Combinational Logic Examples [Verilog]

Logic Design - Combinational Logic Examples [Verilog]

Full-on combinational logic implementation examples in the HDL language Verilog

drifter1

Programming & Dev

2021-07-05 16:51

Logic Design - Combinational Logic in Verilog

Logic Design - Combinational Logic in Verilog

An article on the various ways of modeling and writing combinational logic using Verilog

drifter1

Programming & Dev

2021-06-29 13:01

Logic Design - Verilog Introduction

Logic Design - Verilog Introduction

I'm back guys! This is the first part of my new series on the HDL language Verilog, which is used for hw design and dev.

wiseagent

2026-08-07 19:51

MOVIE REVIEW: “Compliance” (2012)

MOVIE REVIEW: “Compliance” (2012)

This publication was also writen in SPANISH and PORTUGUESE. IMDb Synopsis: When one of the employees at a fast-food chain is “formally” accused of stealing money from a customer's purse, an ordinary workday

hafyan

2018-08-12 20:52

High Cholesterol (Hypercholesterolemia)

High Cholesterol (Hypercholesterolemia)

What Is It? Hypercholesterolemia is a condition characterized by very high levels of cholesterol in the blood. Cholesterol is a waxy, fat-like substance that is produced in the body and obtained from foods

lovelydevil

2018-05-10 12:17

Waiting for the hotpot

Waiting for the hotpot

trikpomkposhishi

2018-02-15 16:24

Alternative ways to reduce cholesterol without drugs

Alternative ways to reduce cholesterol without drugs

Cholesterol is a wax-like substance this is gift inside the cell membranes of body tissues and is carried inside the blood plasma. it's far a sterol; a combination of alcohol and steroid and is likewise

stepin2017

2017-11-08 05:58

Healthiest Foods on the Planet

Healthiest Foods on the Planet

Lemons Why They're Healthy: — Just one lemon has more than 100 percent of your daily intake of vitamin C, which may help increase "good" HDL cholesterol levels and strengthen bones. — Citrus