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latest #hdl created topics | Ecency

piotrgrafik

2y

LDL vs. HDL: The Battle of the Cholesterols Explained

LDL vs. HDL: The Battle of the Cholesterols Explained

Okay, so cholesterol might sound like the bad guy in your body’s health drama, but it’s actually a VIP player that just needs a little balance. The stars of this show are two types of lipoproteins: LDL

$ 3.622

45

drifter1

5y

Logic Design - From Verilog To SystemVerilog

Logic Design - From Verilog To SystemVerilog

The first part of another series where we will be extending our Verilog knowledge into SystemVerilog

$ 2.250

19

drifter1

5y

Logic Design - Switch Level Modeling [Verilog]

Logic Design - Switch Level Modeling [Verilog]

Modeling in the transistor / switch levels using Verilog

drifter1

5y

Logic Design - Compiler Directives [Verilog]

Logic Design - Compiler Directives [Verilog]

In-depth usage guide on the Compiler Directives of Verilog

cliffblank

12d

Dropping Some Love (and BLANK Tokens!) directly to You Legendary Hive Peeps 🚀📦

Dropping Some Love (and BLANK Tokens!) directly to You Legendary Hive Peeps 🚀📦

Dropping Some Love (and BLANK Tokens!) directly to You Legendary Hive Peeps 🚀📦 If you’ve been hanging around my blog, upvoting my posts, leaving thoughtful comments, or just quietly doing your part to

drifter1

5y

Logic Design - Module Parameters and Generate Block [Verilog]

Logic Design - Module Parameters and Generate Block [Verilog]

In-depth guide to Module Parameters and the Generate Block in Verilog HDL

drifter1

5y

Logic Design - Functions and Tasks [Verilog]

Logic Design - Functions and Tasks [Verilog]

In-depth guide on using Functions and Tasks in Verilog

drifter1

5y

Logic Design - Sequential Logic Testbench Example [Verilog]

Logic Design - Sequential Logic Testbench Example [Verilog]

A simple, full-on example of implementing, simulating and verifying a sequence detector FSM

drifter1

5y

Logic Design - Combinational Logic Testbench Example [Verilog]

Logic Design - Combinational Logic Testbench Example [Verilog]

A simple, full-on example of implementing, simulating and verifying a half adder circuit

jongolson

1d

I Pity The Pity Party

I Pity The Pity Party

I am having a hard time choosing a title for this blog post. I want this to be simple, but still come across as a topic that is important for anyone on their journey. We will work through the most, and

drifter1

Programming & Dev

5y

Logic Design - Testbenches and Simulation in Verilog

Logic Design - Testbenches and Simulation in Verilog

In-depth guide on testbench design using Verilog

drifter1

Programming & Dev

5y

Logic Design - Finite-State Machine Examples in Verilog

Logic Design - Finite-State Machine Examples in Verilog

In-depth examples on FSM modeling using the Verilog HDL

drifter1

Programming & Dev

5y

Logic Design - Finite-State Machines in Verilog

Logic Design - Finite-State Machines in Verilog

In-depth guide to modeling any kind of FSM in Verilog using always blocks

drifter1

Programming & Dev

5y

Logic Design - Sequential Logic Examples in Verilog

Logic Design - Sequential Logic Examples in Verilog

Full-on sequential logic implementation examples in Verilog (Flip Flops, Counters and RAM)

onemoretea

2d

The Moon, hmm, Beautiful! - My Actifit Report Card: September 1st, 2026

The Moon, hmm, Beautiful! - My Actifit Report Card: September 1st, 2026

Welcome to Liquid Eye’s Actifit Blog Tuesday ☀️ 13320 A damp, windy, but not really cold morning, once again with relatively high humidity and a dramatic sky. Fall is coming fast. Once again, just a quick,

drifter1

Programming & Dev

5y

Logic Design - Sequential Logic in Verilog

Logic Design - Sequential Logic in Verilog

An article on the various important things to consider when writing sequential logic using Verilog

drifter1

Programming & Dev

5y

Logic Design - Combinational Logic Examples [Verilog]

Logic Design - Combinational Logic Examples [Verilog]

Full-on combinational logic implementation examples in the HDL language Verilog

drifter1

Programming & Dev

5y

Logic Design - Combinational Logic in Verilog

Logic Design - Combinational Logic in Verilog

An article on the various ways of modeling and writing combinational logic using Verilog

drifter1

Programming & Dev

5y

Logic Design - Verilog Introduction

Logic Design - Verilog Introduction

I'm back guys! This is the first part of my new series on the HDL language Verilog, which is used for hw design and dev.

tonyz

Photography Lovers

2d

Broken Face.

As seen in Amsterdam. You can discover a lot by just walking the streets and keeping your eyes open.

hafyan

8y

High Cholesterol (Hypercholesterolemia)

High Cholesterol (Hypercholesterolemia)

What Is It? Hypercholesterolemia is a condition characterized by very high levels of cholesterol in the blood. Cholesterol is a waxy, fat-like substance that is produced in the body and obtained from foods

lovelydevil

8y

Waiting for the hotpot

Waiting for the hotpot

trikpomkposhishi

9y

Alternative ways to reduce cholesterol without drugs

Alternative ways to reduce cholesterol without drugs

Cholesterol is a wax-like substance this is gift inside the cell membranes of body tissues and is carried inside the blood plasma. it's far a sterol; a combination of alcohol and steroid and is likewise

stepin2017

9y

Healthiest Foods on the Planet

Healthiest Foods on the Planet

Lemons Why They're Healthy: — Just one lemon has more than 100 percent of your daily intake of vitamin C, which may help increase "good" HDL cholesterol levels and strengthen bones. — Citrus