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drifter1

2022-02-16 10:10

Logic Design - Circuit Examples in SystemVerilog

Logic Design - Circuit Examples in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic

$ 2.379

64

drifter1

2022-02-10 10:35

Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Command Line Arguments & Dynamic Casting. These are

$ 1.239

40

drifter1

2022-02-07 09:45

Logic Design - Assertions in SystemVerilog

Logic Design - Assertions in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Assertions. So, without further ado, let's get straight

drifter1

2022-02-03 13:41

Logic Design - Functional Coverage in SystemVerilog

Logic Design - Functional Coverage in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Functional Coverage. So, without further ado, let's get

wiseagent

2026-06-30 14:53

[CONTEST] Scrobble Life: Movies, with memories.

[CONTEST] Scrobble Life: Movies, with memories.

This publication was also writen in SPANISH and PORTUGUESE. UPS Today, I'm writing this post to put into practice an idea that I had been developing for quite some time. However, with the creation of this

drifter1

2022-01-31 11:43

Logic Design - Constraint Types in SystemVerilog (part 2)

Logic Design - Constraint Types in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. This is part 2. You can

drifter1

2022-01-29 11:01

Logic Design - Constraint Types in SystemVerilog (part 1)

Logic Design - Constraint Types in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. The topic will be split

drifter1

2022-01-27 11:03

Logic Design - Constraint Blocks (SystemVerilog)

Logic Design - Constraint Blocks (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraint Blocks. Let's note that we will not cover

drifter1

2022-01-26 10:15

Logic Design - Constraints and Randomization (SystemVerilog)

Logic Design - Constraints and Randomization (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraints and Randomization. So, without further ado,

issymarie2

2026-06-30 01:44

Historias tras el polvo: mi apoyo a Venezuela 🇻🇪 [esp-eng]

Historias tras el polvo: mi apoyo a Venezuela 🇻🇪 [esp-eng]

Bendecida tarde-noche, amigos de @holos-lotus. Esperando que este lunes haya sido un día de inicios y alegría. Del mismo modo, espero que este comienzo de semana sea de recuperación y buenas noticias

drifter1

2022-01-25 10:16

Logic Design - Packages in SystemVerilog

Logic Design - Packages in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Packages. So, without further ado, let's get straight

drifter1

2022-01-24 09:17

Logic Design - Program Blocks in SystemVerilog

Logic Design - Program Blocks in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the Program Block. So, without further ado, let's get

drifter1

2022-01-15 15:30

Logic Design - Classes in SystemVerilog (part 3)

Logic Design - Classes in SystemVerilog (part 3)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 3 and also the final part!

drifter1

2022-01-13 10:07

Logic Design - Classes in SystemVerilog (part 2)

Logic Design - Classes in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 2 and so I highly suggest

ogaaloysius

2026-06-29 15:27

The Truth About Being a Student and Building

The Truth About Being a Student and Building

Being a student is not easy. Being a builder is not easy. But being both at the same time? That's a different level of challenge. Between lectures, assignments, and trying to survive on a small budget

drifter1

2022-01-11 10:58

Logic Design - Classes in SystemVerilog (part 1)

Logic Design - Classes in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to start getting into Classes. The topic will be split into multiple

drifter1

2021-12-23 14:53

Logic Design - Interfaces in SystemVerilog (part 2)

Logic Design - Interfaces in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to continue with Interfaces. This is part 2 and so I highly suggest

drifter1

2021-12-22 10:45

Logic Design - Interfaces in SystemVerilog (part 1)

Logic Design - Interfaces in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Interfaces. The topic will be split into two parts! So, without

drifter1

2021-12-14 12:29

Logic Design - Semaphores and Mailboxes (SystemVerilog)

Logic Design - Semaphores and Mailboxes (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Semaphores and Mailboxes, which are the two other interprocess

ineyashami

2026-06-29 22:46

Trying out "Last Asylum: Plague," a little game that popped up in an ad.

Trying out "Last Asylum: Plague," a little game that popped up in an ad.

Hello everyone. In that search for entertainment and distraction, one of the first options for many is games, whether on a computer, console, or phone, and we tend to get quite immersed in them. The thing

drifter1

2021-12-13 12:05

Logic Design - Events (SystemVerilog)

Logic Design - Events (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Events, which are one of the three main interprocess communication

drifter1

2021-12-07 09:56

Logic Design - Processes (SystemVerilog)

Logic Design - Processes (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Processes. So, without further ado, let's dive straight into

drifter1

2021-12-02 13:21

Logic Design - Control Flow (SystemVerilog)

Logic Design - Control Flow (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover some of the additional Control Flow that it provides. Many

drifter1

2021-11-25 13:31

Logic Design - From Verilog To SystemVerilog

Logic Design - From Verilog To SystemVerilog

The first part of another series where we will be extending our Verilog knowledge into SystemVerilog