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drifter1

5y

Logic Design - Circuit Examples in SystemVerilog

Logic Design - Circuit Examples in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic

$ 2.379

64

drifter1

5y

Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Command Line Arguments & Dynamic Casting. These are

$ 1.239

40

drifter1

5y

Logic Design - Assertions in SystemVerilog

Logic Design - Assertions in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Assertions. So, without further ado, let's get straight

drifter1

5y

Logic Design - Functional Coverage in SystemVerilog

Logic Design - Functional Coverage in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Functional Coverage. So, without further ado, let's get

pouchon

5d

LET'S GIVE UP FOR AUGUST 2026

LET'S GIVE UP FOR AUGUST 2026

drifter1

5y

Logic Design - Constraint Types in SystemVerilog (part 2)

Logic Design - Constraint Types in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. This is part 2. You can

drifter1

5y

Logic Design - Constraint Types in SystemVerilog (part 1)

Logic Design - Constraint Types in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. The topic will be split

drifter1

5y

Logic Design - Constraint Blocks (SystemVerilog)

Logic Design - Constraint Blocks (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraint Blocks. Let's note that we will not cover

drifter1

5y

Logic Design - Constraints and Randomization (SystemVerilog)

Logic Design - Constraints and Randomization (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraints and Randomization. So, without further ado,

oadissin

2d

Have a nice weekend: Diamond III Opened The Gate

Have a nice weekend: Diamond III Opened The Gate

I finally got inside the Diamond League. Splinterlands will get fun from this point. Have a wonderful week. Keep sharing your battles.

drifter1

5y

Logic Design - Packages in SystemVerilog

Logic Design - Packages in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Packages. So, without further ado, let's get straight

drifter1

5y

Logic Design - Program Blocks in SystemVerilog

Logic Design - Program Blocks in SystemVerilog

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the Program Block. So, without further ado, let's get

drifter1

5y

Logic Design - Classes in SystemVerilog (part 3)

Logic Design - Classes in SystemVerilog (part 3)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 3 and also the final part!

drifter1

5y

Logic Design - Classes in SystemVerilog (part 2)

Logic Design - Classes in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 2 and so I highly suggest

borjan

Gaming Photography

1d

DAYS AND NIGHTS IN GALAWAIN'S TUSKS

DAYS AND NIGHTS IN GALAWAIN'S TUSKS

Galawain's Tusks is a volcanic region in the northern part of the Living Lands. It is the most desolate, rugged part of that untamed island. The rocks look like threatening claws, and lava runs through

drifter1

5y

Logic Design - Classes in SystemVerilog (part 1)

Logic Design - Classes in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to start getting into Classes. The topic will be split into multiple

drifter1

5y

Logic Design - Interfaces in SystemVerilog (part 2)

Logic Design - Interfaces in SystemVerilog (part 2)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to continue with Interfaces. This is part 2 and so I highly suggest

drifter1

5y

Logic Design - Interfaces in SystemVerilog (part 1)

Logic Design - Interfaces in SystemVerilog (part 1)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Interfaces. The topic will be split into two parts! So, without

drifter1

5y

Logic Design - Semaphores and Mailboxes (SystemVerilog)

Logic Design - Semaphores and Mailboxes (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Semaphores and Mailboxes, which are the two other interprocess

triverse

1d

Sonic the Hedgehog Demo Lands on Commodore Amiga

Sonic the Hedgehog Demo Lands on Commodore Amiga

You can download and play it right now

drifter1

5y

Logic Design - Events (SystemVerilog)

Logic Design - Events (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Events, which are one of the three main interprocess communication

drifter1

5y

Logic Design - Processes (SystemVerilog)

Logic Design - Processes (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Processes. So, without further ado, let's dive straight into

drifter1

5y

Logic Design - Control Flow (SystemVerilog)

Logic Design - Control Flow (SystemVerilog)

[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover some of the additional Control Flow that it provides. Many

drifter1

5y

Logic Design - From Verilog To SystemVerilog

Logic Design - From Verilog To SystemVerilog

The first part of another series where we will be extending our Verilog knowledge into SystemVerilog