#risc-v

Pawel Czerwinski | Unsplash Ethereum to this day remains an incredible technology, although there is a discussion addressing the unrealization of its potential. While Bitcoin seems to outperform time and

Ethereum co-founder Vitalik Buterin has proposed a significant change to the network's architecture: replacing the Ethereum Virtual Machine (EVM) with RISC-V, an open-source instruction set architecture.

Risc-V is currently very bad in performance. Mainly because only the CPU arch is free. this means that any company can print this CPUs, without needing any architecture engineer. But a PC is not just a

Emerging AI and chip standards technology.

Armbian 作为基于 Ubuntu 和 Debian 的 Linux 发行版，主要针对 ARM/AArch64 和 RISC-V 空间中的单板计算机进行了优化，并于 2023 年发布了第一个重大更新。Armbian 23.02 作为此 ARM /以 RISC-V 为导向的 Linux 发行版，它是向 Linux 6.1 LTS 内核的迁移，以提供更新的 SoC 和平台支持，以及其他内核改进。 Armbian

Think Silicon 展示了首款量产 RISC-V 3D GPU 设计。 Think Silicon NEOX G 系列和 A 系列是他们首款基于 RISC-V 的低功耗 GPU 设计。在 Think Silicon宣布嵌入式世界演示 的新闻稿中，他们解释说： NEOX™| G（图形）和 A（深度学习加速器）系列 IP 代表了智能 GPU 架构的新时代，可编程计算着色器在实时操作系统 (RTOS)

Alibaba unveiled Xuantie-910 RISC-V core (aka XT910) in 2019 for powerful SoC with up to 16 cores, but an update in 2020 revealed the company planned to have a complete RISC-V core family for a wide range

We first covered zGlue's ZiP (zGlue Integration Platform) in 2018 as the company introduced its multi-chip module similar to SiP (system-in-package) via a crowdfunding campaign. Just like SiP, the technology

Efinix has announced three RISC-V Software-defined SoC's based on Charles Papon's VexRiscv core and optimized for the company's Trion T8 to T120 FPGA's. VexRiscv is a 32-bit RISC-V CPU using  RISCV32I

<br TTGO T-Watch K210 AIOT - Click to Enlarge After covering ESP32 based TTGO T-Watch-2020 programmable watch last month, I noticed LilyGO launched "TTGO T-Watch K210 AIOT" watch with Kendryte

CNXSoft: This is a guest post by RT-Thread explaining how to create your first program running on their real-time operating system using a GD32V  RISC-V MCU board as an example. This article describes

Introduced in 2018, ZiP (zGlue Integration Platform) chip-stacking technology aims to produce chips similar to Systems-in-Package (SiP) but at much lower costs and lead times. We first found it in a Bluetooth

A few months ago, we wrote that Western Digital was working on Linux & BusyBox RISC-V NOMMU, and managed to boot a minimal Linux OS on Kendryte K210 powered Sipeed Maix Go board. RISC-V NOMMU support

FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled "Open ESP � The Heterogeneous Open-Source

AndesCore 27-Series VPU Andes has developed a Linux capable RISC-V based SoC which runs on the first Vector Processing Unit (VPU) that is reported to be groundbreaking in its application ability, especially

The other days we wrote about Getting Started with Embedded Linux on RISC-V in QEMU emulator and noted that currently Linux capable RISC-V hardware is fairly expensive. We also mentioned there was work

Recently we highlighted the $5 Longan Nano, a development kit released by Sipeed for the Gigadevice GD32V RISC-V family of microcontrollers. The Sipeed Longan Nano is powered by the GigaDevice's GD32VF103CBT6,

Earlier this week, we wrote about SiFive Shield open security platform as the equivalent of Arm TrustZone security technology, but the company had had another important announcement this week with the

The European Union's consortium to develop European microprocessors for future supercomputers has taken a few more steps towards its goal of delivering a locally made exascale chip by 2025. That is why,