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Introduction
Hey it's a me again @drifter1!
Today we continue with the Logic Design series on Verilog to cover Compiler Directives, some of which have already been covered in previous parts of the series.
So, without further ado, let's dive more into it!
Compiler Directives
Compiler Directives:
- begin with the grave accent (`)
- don't end with a semi-colon (;)
- aren't bound by modules or by files, and
- their effect lasts from the place in the source code they are defined, throughout the files processed afterwards, and up to the point they are superseded or at the end of the last file that's processed
Include
Using the include directive, source code from another Verilog file is included in the currently processed file.
Its syntax is:
`include "file_name"
For example:
`include "/common/definitions.v"
Text Macros (define, undef)
Using the define directive one may define text macros, which can be used in order to improve the readability and maintainability of the Verilog code. These macros can also be parameterized quite easily.
A macro definition looks like this:
`define macro_name macro_code
`define macro_name ([parameter_list]) macro_code
For example:
`define CLK_PERIOD 10
In order to cancel a macro definition undef is used, which has the following syntax:
`undef macro_name
Timescale
With a timescale directive we define the simulation time unit and precision for the delays. This unit specifies a #1 of delay. The time base can be s, ms, us, ns, ps or fs. All delays are delayed to the nearest precision, and thus the precision must be less than or equal to the unit.
The syntax is:
`timescale unit base / precision base
For example:
`timescale 1ns/1ps
Conditional Compilation (ifdef, ifndef)
Using the ifdef, ifndef etc. directives one may conditionally compile Verilog code based on the definition of a macro or not. Of course all of the code must still be valid Verilog code!
Its syntax is:
`ifdef macro_name OR `ifndef macro_name
// Verilog code
`elsif
// Verilog code
`else
// Verilog code
`endif
where the elsif's and else can of course be omitted.
Library Cells (celldefine, endcelldefine)
Using celldefine and endcelldefine one may mark the module(s) as a library cell, as follows:
`celldefine
// module(s)
`endcelldefine
Line
Using the line directive one may specify the original source code's line number and filename. The location in the original file is maintained if another process modifies its source.
The syntax is:
`line line_number "file_name" level
The level part of the directive specifies whether an include file has been entered (1), an include file is exited (2), or neither (0).
Overriding and Reseting Defaults (default_nettype, reset_all)
Implicitly the default net data type is wire. This can be changed specifying the default_nettype directive, as follows:
`default_nettype net_data_type
The valid types are: wire, tri, tri0, tri1, triand, trior, trireg, wand, wor, none.
Using the reset_all directive all active compiler directives that have a default value are reset back to that default value.
The syntax is simply:
`reset_all
Others
There are tons more, and it might even be impossible to cover them all. Here's a list of some of them:
`unconnected_drive pull0 // set unconnected inputs to 0
`unconnected_drive pull1 // set unconnected inputs to 1
`nounconnected_drive // terminates either of the above directives
`default_decay_time a_time // sets all undefined trireg net decay times,
// a_time is integer, real or infinite
`default_trireg_strength val // default trireg net strength 0 to 250
`delay_mode_distributed // sets distributed delay mode
`delay_mode_path // sets path delay mode
`delay_mode_unit // sets unit delay mode
`delay_mode_zero // sets zero-delay mode
directly taken from Reference 5.
RESOURCES:
References
- http://www.asic-world.com/verilog/veritut.html
- https://www.chipverify.com/verilog/verilog-tutorial
- https://www.javatpoint.com/verilog
- https://www.hdlworks.com/hdl_corner/verilog_ref/items/CompilerDirectives.htm
- https://www.csee.umbc.edu/portal/help/VHDL/verilog/compiler.html
Images
Block diagrams and other visualizations were made using draw.io
Previous articles of the series
- Introduction → Basic Syntax, Data Types, Operators, Modules
- Combinational Logic → Assign Statement, Always Block, Control Blocks, Gate-Level Modeling and Primitives, User-Defined Primitives
- Combinational Logic Examples → One Circuit - Four Implementations, Encoder, Decoder, Multiplexer
- Sequential Logic → Procedural Blocks (Initial, Always), Blocking and Non-Blocking Assignments, Statement Groups
- Sequential Logic Examples → Flip Flops (DFF, TFF, JKFF, SRFF), N-bit Counter, Single-Port RAM
- Finite-State Machines → Finite-State Machine (FSM), FSM Types, State Encoding, Modeling FSMs in Verilog
- Finite-State Machine Examples → Moore FSM Example (1 and 2 always blocks), Mealy FSM Example (1, 2 and 3 always blocks)
- Testbenches and Simulation → Testbenches (DUT / UUT, Syntax, Test Cases), System Tasks, Simulation Tools
- Combinational Logic Testbench Example → Half Adder Implementation, Testbench and Simulation
- Sequential Logic Testbench Example → Sequence Detector FSM Implementation, Testbench and Simulation
- Functions and Tasks → Function and Task Syntax, Calling, Rules, Examples
- Module Parameters and Generate Block → Parameterized Module (Parameters, Instantiation and Overriding Parameters), Generate Blocks (For, If, Case)
Final words | Next up
And this is actually it for today's post!
Next time we will cover Switch Level Modeling in Verilog, which might even be the final part before SystemVerilog!
See Ya!
Keep on drifting!