EU plans for domestic exascale supercomputer chips based on Risc-V open source ISA

The European Union's consortium to develop European microprocessors for future supercomputers has taken a few more steps towards its goal of delivering a locally made exascale chip by 2025.

That is why, as part of this consortium, we are going to start our own processor development which is based on RISC-V, and develop some IP and ecosystem around it. We do not start from zero, because there is some instruction set and elements which are ready. Unfortunately, it is not at HPC production level yet and it will take a couple of generations.”

The Euro exascale system will use off-the-shelf memory (HBM3) but European-developed memory controller, Network-On-Chip (NOC), interconnect and power management technology. Nothing has yet been said about storage and its software. The EPI aspect is restricted to the processors, low level software, like an SDK, and compilers.

Source:
https://www.theregister.co.uk/2018/07/17/europes_exascale_supercomputer_chips/

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