NAND Flash memory uses cells typically formed by NPN transistors in which the gate (gate) are due to oxide layer trapped electrons forming the charge of the memory cells, according to which, according to different levels to determine the three recorded bits. We can find nothing of this in memory 3D XPOINT, because they are not based on transistors, but on something else.
3D XPoint [http://www.intelfreepress.com]
Manufacturers talks about the so-called "Crosspoint structure". Silver-colored wires formes a reticulated structure, which allows exactly address a single memory cell. Just to pick two wires of adjacent layers that intersect precisely in the desired memory cell shown in green and yellow bar. With this structure it will be theoretically very easy to add new layers, making the chip capacity increase by the equivalent of the base layer.
In short, the memory function is, that the voltage is applied to the so-called wordline and bitline, the two conductors intersecting at the point of the intended memory cell. It then either causes the cell state reading or writing of zeros or ones. Applied voltage have to be to be significantly lower than that used in the case of NAND Flash, so that it will be substantially less than 20 V and therefore the devices with 3D XPOINT should be economical.
Already manufactured memory 3D XPOINT have two layers, each having a capacity of 64 GB. Total chip thus has a 128 Gb, or 16 GB, and here we see great potential for the future. However, if manufacturers already producing 32 or handle 48vrstvých NAND Flash, which are more complex transistor structures, then it would logically not be a problem to make or 3D XPOINT such a number of layers. So if we count with 48 layers, each with 64 Gb, then such a chip would be offered a full 384 GB of capacity.
