<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>https://ecency.com</link><image><url>https://ecency.com/logo512.png</url><title>RSS Feed</title><link>https://ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Thu, 15 Oct 2026 13:54:24 GMT</lastBuildDate><atom:link href="https://ecency.com/created/onehot/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Logic Design - Statetable Simplification and Implementation with one-hot encoding]]></title><description><![CDATA[    Hey it's me again! Today we will talk about a Statetable Simplification Method and afterwards we will implement the Sequential Circuit of our Example in one-hot encoding using D]]></description><link>https://ecency.com/@drifter1/logic-design-statetable-simplification-and-implementation-with-one-hot-encoding</link><guid isPermaLink="true">https://ecency.com/@drifter1/logic-design-statetable-simplification-and-implementation-with-one-hot-encoding</guid><category><![CDATA[logic]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 13 Sep 2017 13:49:03 GMT</pubDate><enclosure url="https://i.ecency.com/p/9RTqgzgfVW72JCGf9mH9dnoYDXz1VvdQWXmcbNAUVNZNtG2RsG7HuydiEWnBbo64bipfqWNppE?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>