<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>https://ecency.com</link><image><url>https://ecency.com/logo512.png</url><title>RSS Feed</title><link>https://ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Sun, 23 Aug 2026 11:26:07 GMT</lastBuildDate><atom:link href="https://ecency.com/created/mealy/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Logic Design - Finite-State Machine Examples in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Finite-State Machine Examples. There will be one FSM for each type (Moore,]]></description><link>https://ecency.com/@drifter1/logic-design-finite-state-machine-examples-in-verilog</link><guid isPermaLink="true">https://ecency.com/@drifter1/logic-design-finite-state-machine-examples-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 04 Oct 2021 12:15:48 GMT</pubDate><enclosure url="https://i.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Finite-State Machines in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Finite-State Machines (FSMs). The article will start out with a small]]></description><link>https://ecency.com/@drifter1/logic-design-finite-state-machines-in-verilog</link><guid isPermaLink="true">https://ecency.com/@drifter1/logic-design-finite-state-machines-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 21 Sep 2021 09:35:27 GMT</pubDate><enclosure url="https://i.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>